/*
┌───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────┐
│                                                                                                                       │
│               Project: PC_cntr_tb                                                                                     │
│                Author: Michael Krämer                                                                                 │
│                        Michael@dk8pp.de                                                                               │
│                  Date: 14.11.2024                                                                                     │
│              Language: Verilog                                                                                        │
│               Version: 0.1                                                                                            │
│         Design status: first try                                                                                      │
│                Device: EPM7064STC44-7 (discontinued, only for proof-of-concept with prototype)                        │
│                                                                                                                       │
├───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────┤
│                                                                                                                       │
│  Purpose: Testbench for counter of PhaseComparator.                                                                   │
│                                                                                                                       │
└───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────┘
*/

/*
┌───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────┐
│       Module: PC_cntr_tb                                                                                              │
└───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────┘
*/
module PC_cntr_tb ;
                reg clkuf ;             /* input clock from forward port */
                reg clkur ;             /* input clock from reflected port */
                reg enable ;            /* enable operation when high, reset when low */
                reg [3:0] sel ;         /* select counter bit for reading by CPU, 0:cntr[0], ... 15:cntr[15] */
                reg gate_timer ;        /* gate signal for counter, active high, in the order of 1 ms */
                reg reset_counter ;     /* asynchronous reset counter on rising edge */
                wire dataout ;          /* data output for reading the counter */
                wire clkactive ;        /* clkur is active if high */
                wire ur_leading ;       /* high if clkur is leading clkuf, low otherwise */
                wire pwm ;              /* pwm encoded phase delay */
                reg [4:1] dsw ;         /* dip-switch inputs */
                wire [7:0] la ;         /* logic analyser outputs */
                wire shdn ;             /* shutdown output for comparators */
                wire ena ;              /* enable output for log amp */
                wire led ;              /* LED output */
                reg res0 ;              /* reserved pins defined as inputs */
                reg res2 ;              /* reserved pins defined as inputs */
                reg res3 ;              /* reserved pins defined as inputs */
                wire res4 ;             /* reserved output */

/*
┌───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────┐
│       registers and wires                                                                                             │
└───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────┘
*/

PhaseComparator
      pcomp (.clkuf (clkuf),
             .clkur (clkur),
             .enable (enable),
             .sel (sel),
             .gate_timer (gate_timer),
             .reset_counter (reset_counter),
             .dataout (dataout),
             .clkactive (clkactive),
             .ur_leading (ur_leading),
             .pwm (pwm),
             .dsw (dsw),
             .la (la),
             .shdn (shdn),
             .ena (ena),
             .led (led),
             .res0 (res0),
             .res2 (res2),
             .res3 (res3),
             .res4 (res4)
             ) ;

initial
begin
   reset_all() ;
   #500 gate_timer = 0 ;
   readcntr() ;
   #102 reset_counter = 1 ;
   #20 reset_counter = 0 ;
   #100 pcomp.cntr = 16'haaaa ;
   readcntr() ;

   #100 ;

   $stop(2) ;
end

   always begin
      #5 clkuf = 1 ;
      #5 clkuf = 0 ;
   end

   task readcntr() ;
   integer i ;
   begin
      for (i=0; i<16; i = i + 1)
      begin
         sel = i ;
         #25 ;
      end
   end
   endtask

   task reset_all() ;
   begin
      enable = 0 ;
      clkuf = 0 ;
      sel = 4'b0000 ;
      reset_counter = 0 ;
      pcomp.cntr = 16'h1234 ;
      gate_timer = 0 ;
      #10 enable = 1 ;
      #20 reset_counter = 1 ;
      #30 reset_counter = 0 ;
      #40 gate_timer = 1 ;
   end
   endtask

endmodule


