Code copied from original Gowin demo code
Modifications:

config.h:
original: #define BUILD_MODE BUILD_BURN         //Must match with hardware IP
changed:  #define BUILD_MODE BUILD_LOAD         //Must match with hardware IP

CPU clock is now 20 MHz from PLL pll_clkout1

project compiled and output converted to hex:
run: <project path>\Release\make_hex.bat to generate "ram32.hex" in the same directory
link to "ram32.hex" is needed by the IP core generator (see below)

HW-project:
select device: GW5A-LV25MG121 Version A

use IP Core Generator to generate new Hard Module/CLOCK/PLL_ADV:
CLKIN frequency: 50 MHz
Enable Lock: yes
2nd Tab (Clkout0):
Expected Frequency: 200 MHz
3rd Tab (clkout1):
Enable CLKOUT1: yes
Expected Frequency: 20 MHz
press "Calculate" and "OK"

use IP Core Generator to generate new Soft IP Core/Microprocessor System/Soft-Core_MPU/Gowin_PicoRV32:
Disable "Use Gowin PicoRV32 as top module"
ITCM 32KB: MCU boot and run in ITCM, init file: ram32.hex (see above)
DTCM 32KB (default)
disable "Simple UART"
enable WB UART
enable Wishbone SPI Master:
Shift direction: 0 (MSB first)
Clock phase: 1, the data is valid on the second edge (falling edge) of the SCLK
Clock polarity: 0, SCLK is low in the idle state
Clock count width: 2 (must be sufficient bit width to satisfy SCLK data width)
Note: max SCLK frequency for ADS1118 is 4 MHz, we select 2.0 MHz at 20 MHz CLK_I
Clock sel: 4, SCLK frequency calculation: SCLK = CLK_I/(2*(CLOCK_SEL+1))
Data Length: 32 bits
Slave number: 1, Specify the supported Slave count
Delay time: 2, delay time to wait before the first data transmission after the SS_N signal is valid, Delay = Delay Time * (SCLK period/2)
Interval length: 2, SCLK cycles to wait for the SS_N signal after SPI transfers the request
enable Open WB Interface

Pin assignments in FloorPlanner: according to schematics, see also file <Signale.ods>
Signals from Tang Primer boards:
xosc: E2 (50 MHz oscillator on Tang Primer board)
reset_in_dock: H11, pull-mode: DOWN, (Pushbutton S1 on Dock Board)

unused for now:
jtag_TMS: B11 (unused)
jtag_TDO: C11 (unused)
jtag_TDI: D11 (unused)
jtag_TCK: E11 (unused)

Configuration settings as required.
suggestion: Unused pins: as input tri-stated with pull-up (default)
Route Option 2 may increase max speed by about 10%

Suggestion for timing simulation:
Set False Path:
From: -
Trough: -
To: PicoRV32/wb/mem_rdata*/D
This prevents false report of timing violations when reading RefMeas registers,
which must only be read when measurement is idle.

Programmer setup for SRAM programming: SRAM Mode, SRAM Program
programming takes about 5 seconds

Programmer setup for Flash programming: External Flash Mode 5A, exFlash Erase, Program, Verify 5A
programming takes about 150 seconds


