Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Program Files\Gowin\Gowin_V1.9.11.01_Education_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picorv32.v C:\Program Files\Gowin\Gowin_V1.9.11.01_Education_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc.v C:\Program Files\Gowin\Gowin_V1.9.11.01_Education_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\advspi.v C:\Program Files\Gowin\Gowin_V1.9.11.01_Education_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\ahb_bus.v C:\Program Files\Gowin\Gowin_V1.9.11.01_Education_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_dtcm.v C:\Program Files\Gowin\Gowin_V1.9.11.01_Education_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_itcm.v C:\Program Files\Gowin\Gowin_V1.9.11.01_Education_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_bus.v C:\Program Files\Gowin\Gowin_V1.9.11.01_Education_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_brancher.v C:\Program Files\Gowin\Gowin_V1.9.11.01_Education_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbgpio.v C:\Program Files\Gowin\Gowin_V1.9.11.01_Education_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbi2c.v C:\Program Files\Gowin\Gowin_V1.9.11.01_Education_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbspi.v C:\Program Files\Gowin\Gowin_V1.9.11.01_Education_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbuart.v C:\Program Files\Gowin\Gowin_V1.9.11.01_Education_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\simpleuart.v C:\Program Files\Gowin\Gowin_V1.9.11.01_Education_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\dm.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.01 Education (64-bit) |
| Part Number | GW5A-LV25MG121NC1/I0 |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Thu Jan 8 12:41:23 2026 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Gowin_PicoRV32_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.906s, Elapsed time = 0h 0m 1s, Peak memory usage = 87.227MB Running netlist conversion: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.066s, Peak memory usage = 87.227MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.476s, Peak memory usage = 87.227MB Optimizing Phase 1: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.172s, Peak memory usage = 87.227MB Optimizing Phase 2: CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.625s, Peak memory usage = 87.227MB Running inference: Inferring Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 87.227MB Inferring Phase 1: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.329s, Peak memory usage = 87.227MB Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 87.227MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 87.227MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.656s, Elapsed time = 0h 0m 0.652s, Peak memory usage = 87.227MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.293s, Peak memory usage = 87.227MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.194s, Peak memory usage = 87.227MB Tech-Mapping Phase 3: CPU time = 0h 0m 18s, Elapsed time = 0h 0m 18s, Peak memory usage = 106.094MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.535s, Peak memory usage = 106.094MB Generate output files: CPU time = 0h 0m 0.75s, Elapsed time = 0h 0m 0.762s, Peak memory usage = 137.477MB |
| Total Time and Memory Usage | CPU time = 0h 0m 23s, Elapsed time = 0h 0m 24s, Peak memory usage = 137.477MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 128 |
| I/O Buf | 128 |
| IBUF | 52 |
| OBUF | 76 |
| Register | 3935 |
| DFFSE | 90 |
| DFFRE | 2664 |
| DFFPE | 4 |
| DFFCE | 1177 |
| LUT | 5490 |
| LUT2 | 234 |
| LUT3 | 2012 |
| LUT4 | 3244 |
| ALU | 566 |
| ALU | 566 |
| INV | 18 |
| INV | 18 |
| DSP | |
| MULT27X36 | 2 |
| BSRAM | 32 |
| SDPB | 32 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 6074(5508 LUT, 566 ALU) / 23040 | 27% |
| Register | 3935 / 23280 | 17% |
| --Register as Latch | 0 / 23280 | 0% |
| --Register as FF | 3935 / 23280 | 17% |
| BSRAM | 32 / 56 | 58% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk_in | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_in_ibuf/I | ||
| 2 | jtag_TCK | Base | 10.000 | 100.000 | 0.000 | 5.000 | jtag_TCK_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk_in | 100.000(MHz) | 54.511(MHz) | 11 | TOP |
| 2 | jtag_TCK | 100.000(MHz) | 99.502(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -6.322 |
| Data Arrival Time | 16.634 |
| Data Required Time | 10.311 |
| From | core/mem_addr_26_s0 |
| To | core/mem_rdata_q_23_s0 |
| Launch Clk | clk_in[R] |
| Latch Clk | clk_in[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_in | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3817 | clk_in_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | core/mem_addr_26_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 2 | core/mem_addr_26_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | itcm_valid_s2/I0 |
| 1.659 | 0.526 | tINS | RR | 6 | itcm_valid_s2/F |
| 2.034 | 0.375 | tNET | RR | 1 | itcm_valid_s3/I3 |
| 2.296 | 0.262 | tINS | RR | 4 | itcm_valid_s3/F |
| 2.671 | 0.375 | tNET | RR | 1 | core/n1614_s2/I0 |
| 3.198 | 0.526 | tINS | RR | 5 | core/n1614_s2/F |
| 3.573 | 0.375 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I1 |
| 4.089 | 0.516 | tINS | RR | 41 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
| 4.464 | 0.375 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
| 4.726 | 0.262 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
| 5.101 | 0.375 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
| 5.562 | 0.461 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
| 5.938 | 0.375 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s4/I2 |
| 6.399 | 0.461 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s4/F |
| 6.774 | 0.375 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s1/I0 |
| 6.910 | 0.136 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s1/O |
| 7.285 | 0.375 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s/I1 |
| 7.371 | 0.086 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_26_s/O |
| 7.746 | 0.375 | tNET | RR | 1 | mem_rdata_26_s4/I1 |
| 8.262 | 0.516 | tINS | RR | 1 | mem_rdata_26_s4/F |
| 8.637 | 0.375 | tNET | RR | 1 | mem_rdata_26_s2/I0 |
| 9.164 | 0.526 | tINS | RR | 3 | mem_rdata_26_s2/F |
| 9.539 | 0.375 | tNET | RR | 1 | core/mem_rdata_latched_10_s8/I1 |
| 10.055 | 0.516 | tINS | RR | 3 | core/mem_rdata_latched_10_s8/F |
| 10.430 | 0.375 | tNET | RR | 1 | core/n5637_s8/I1 |
| 10.946 | 0.516 | tINS | RR | 1 | core/n5637_s8/F |
| 11.321 | 0.375 | tNET | RR | 1 | core/n5637_s7/I2 |
| 11.782 | 0.461 | tINS | RR | 3 | core/n5637_s7/F |
| 12.157 | 0.375 | tNET | RR | 1 | core/n5637_s4/I1 |
| 12.674 | 0.516 | tINS | RR | 11 | core/n5637_s4/F |
| 13.049 | 0.375 | tNET | RR | 1 | core/n2083_s12/I0 |
| 13.575 | 0.526 | tINS | RR | 2 | core/n2083_s12/F |
| 13.950 | 0.375 | tNET | RR | 1 | core/n2083_s5/I1 |
| 14.466 | 0.516 | tINS | RR | 1 | core/n2083_s5/F |
| 14.841 | 0.375 | tNET | RR | 1 | core/n2083_s1/I1 |
| 15.357 | 0.516 | tINS | RR | 1 | core/n2083_s1/F |
| 15.732 | 0.375 | tNET | RR | 1 | core/n2083_s0/I0 |
| 16.259 | 0.526 | tINS | RR | 1 | core/n2083_s0/F |
| 16.634 | 0.375 | tNET | RR | 1 | core/mem_rdata_q_23_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_in | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 3817 | clk_in_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | core/mem_rdata_q_23_s0/CLK |
| 10.311 | -0.064 | tSu | 1 | core/mem_rdata_q_23_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 18 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 8.376, 51.518%; route: 7.500, 46.129%; tC2Q: 0.382, 2.353% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:| Slack | -6.267 |
| Data Arrival Time | 16.579 |
| Data Required Time | 10.311 |
| From | core/mem_addr_26_s0 |
| To | core/mem_rdata_q_22_s0 |
| Launch Clk | clk_in[R] |
| Latch Clk | clk_in[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_in | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3817 | clk_in_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | core/mem_addr_26_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 2 | core/mem_addr_26_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | itcm_valid_s2/I0 |
| 1.659 | 0.526 | tINS | RR | 6 | itcm_valid_s2/F |
| 2.034 | 0.375 | tNET | RR | 1 | itcm_valid_s3/I3 |
| 2.296 | 0.262 | tINS | RR | 4 | itcm_valid_s3/F |
| 2.671 | 0.375 | tNET | RR | 1 | core/n1614_s2/I0 |
| 3.198 | 0.526 | tINS | RR | 5 | core/n1614_s2/F |
| 3.573 | 0.375 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I1 |
| 4.089 | 0.516 | tINS | RR | 41 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
| 4.464 | 0.375 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
| 4.726 | 0.262 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
| 5.101 | 0.375 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
| 5.562 | 0.461 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
| 5.938 | 0.375 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s4/I2 |
| 6.399 | 0.461 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s4/F |
| 6.774 | 0.375 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s1/I0 |
| 6.910 | 0.136 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s1/O |
| 7.285 | 0.375 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s/I1 |
| 7.371 | 0.086 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_26_s/O |
| 7.746 | 0.375 | tNET | RR | 1 | mem_rdata_26_s4/I1 |
| 8.262 | 0.516 | tINS | RR | 1 | mem_rdata_26_s4/F |
| 8.637 | 0.375 | tNET | RR | 1 | mem_rdata_26_s2/I0 |
| 9.164 | 0.526 | tINS | RR | 3 | mem_rdata_26_s2/F |
| 9.539 | 0.375 | tNET | RR | 1 | core/mem_rdata_latched_10_s8/I1 |
| 10.055 | 0.516 | tINS | RR | 3 | core/mem_rdata_latched_10_s8/F |
| 10.430 | 0.375 | tNET | RR | 1 | core/n5637_s8/I1 |
| 10.946 | 0.516 | tINS | RR | 1 | core/n5637_s8/F |
| 11.321 | 0.375 | tNET | RR | 1 | core/n5637_s7/I2 |
| 11.782 | 0.461 | tINS | RR | 3 | core/n5637_s7/F |
| 12.157 | 0.375 | tNET | RR | 1 | core/n5637_s4/I1 |
| 12.674 | 0.516 | tINS | RR | 11 | core/n5637_s4/F |
| 13.049 | 0.375 | tNET | RR | 1 | core/n2083_s12/I0 |
| 13.575 | 0.526 | tINS | RR | 2 | core/n2083_s12/F |
| 13.950 | 0.375 | tNET | RR | 1 | core/n2084_s4/I1 |
| 14.466 | 0.516 | tINS | RR | 1 | core/n2084_s4/F |
| 14.841 | 0.375 | tNET | RR | 1 | core/n2084_s2/I0 |
| 15.367 | 0.526 | tINS | RR | 1 | core/n2084_s2/F |
| 15.742 | 0.375 | tNET | RR | 1 | core/n2084_s0/I2 |
| 16.204 | 0.461 | tINS | RR | 1 | core/n2084_s0/F |
| 16.579 | 0.375 | tNET | RR | 1 | core/mem_rdata_q_22_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_in | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 3817 | clk_in_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | core/mem_rdata_q_22_s0/CLK |
| 10.311 | -0.064 | tSu | 1 | core/mem_rdata_q_22_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 18 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 8.321, 51.353%; route: 7.500, 46.286%; tC2Q: 0.382, 2.361% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:| Slack | -6.203 |
| Data Arrival Time | 16.514 |
| Data Required Time | 10.311 |
| From | core/mem_addr_26_s0 |
| To | core/mem_rdata_q_21_s0 |
| Launch Clk | clk_in[R] |
| Latch Clk | clk_in[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_in | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3817 | clk_in_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | core/mem_addr_26_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 2 | core/mem_addr_26_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | itcm_valid_s2/I0 |
| 1.659 | 0.526 | tINS | RR | 6 | itcm_valid_s2/F |
| 2.034 | 0.375 | tNET | RR | 1 | itcm_valid_s3/I3 |
| 2.296 | 0.262 | tINS | RR | 4 | itcm_valid_s3/F |
| 2.671 | 0.375 | tNET | RR | 1 | core/n1614_s2/I0 |
| 3.198 | 0.526 | tINS | RR | 5 | core/n1614_s2/F |
| 3.573 | 0.375 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I1 |
| 4.089 | 0.516 | tINS | RR | 41 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
| 4.464 | 0.375 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
| 4.726 | 0.262 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
| 5.101 | 0.375 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
| 5.562 | 0.461 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
| 5.938 | 0.375 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s4/I2 |
| 6.399 | 0.461 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s4/F |
| 6.774 | 0.375 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s1/I0 |
| 6.910 | 0.136 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s1/O |
| 7.285 | 0.375 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s/I1 |
| 7.371 | 0.086 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_26_s/O |
| 7.746 | 0.375 | tNET | RR | 1 | mem_rdata_26_s4/I1 |
| 8.262 | 0.516 | tINS | RR | 1 | mem_rdata_26_s4/F |
| 8.637 | 0.375 | tNET | RR | 1 | mem_rdata_26_s2/I0 |
| 9.164 | 0.526 | tINS | RR | 3 | mem_rdata_26_s2/F |
| 9.539 | 0.375 | tNET | RR | 1 | core/mem_rdata_latched_10_s8/I1 |
| 10.055 | 0.516 | tINS | RR | 3 | core/mem_rdata_latched_10_s8/F |
| 10.430 | 0.375 | tNET | RR | 1 | core/n5637_s8/I1 |
| 10.946 | 0.516 | tINS | RR | 1 | core/n5637_s8/F |
| 11.321 | 0.375 | tNET | RR | 1 | core/n5637_s7/I2 |
| 11.782 | 0.461 | tINS | RR | 3 | core/n5637_s7/F |
| 12.157 | 0.375 | tNET | RR | 1 | core/n5231_s15/I1 |
| 12.674 | 0.516 | tINS | RR | 2 | core/n5231_s15/F |
| 13.049 | 0.375 | tNET | RR | 1 | core/n2082_s10/I2 |
| 13.510 | 0.461 | tINS | RR | 1 | core/n2082_s10/F |
| 13.885 | 0.375 | tNET | RR | 1 | core/n2082_s5/I1 |
| 14.401 | 0.516 | tINS | RR | 4 | core/n2082_s5/F |
| 14.776 | 0.375 | tNET | RR | 1 | core/n2085_s1/I2 |
| 15.237 | 0.461 | tINS | RR | 2 | core/n2085_s1/F |
| 15.612 | 0.375 | tNET | RR | 1 | core/n2085_s0/I0 |
| 16.139 | 0.526 | tINS | RR | 1 | core/n2085_s0/F |
| 16.514 | 0.375 | tNET | RR | 1 | core/mem_rdata_q_21_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_in | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 3817 | clk_in_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | core/mem_rdata_q_21_s0/CLK |
| 10.311 | -0.064 | tSu | 1 | core/mem_rdata_q_21_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 18 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 8.256, 51.158%; route: 7.500, 46.472%; tC2Q: 0.382, 2.370% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:| Slack | -6.203 |
| Data Arrival Time | 16.514 |
| Data Required Time | 10.311 |
| From | core/mem_addr_26_s0 |
| To | core/mem_rdata_q_20_s0 |
| Launch Clk | clk_in[R] |
| Latch Clk | clk_in[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_in | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3817 | clk_in_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | core/mem_addr_26_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 2 | core/mem_addr_26_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | itcm_valid_s2/I0 |
| 1.659 | 0.526 | tINS | RR | 6 | itcm_valid_s2/F |
| 2.034 | 0.375 | tNET | RR | 1 | itcm_valid_s3/I3 |
| 2.296 | 0.262 | tINS | RR | 4 | itcm_valid_s3/F |
| 2.671 | 0.375 | tNET | RR | 1 | core/n1614_s2/I0 |
| 3.198 | 0.526 | tINS | RR | 5 | core/n1614_s2/F |
| 3.573 | 0.375 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I1 |
| 4.089 | 0.516 | tINS | RR | 41 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
| 4.464 | 0.375 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
| 4.726 | 0.262 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
| 5.101 | 0.375 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
| 5.562 | 0.461 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
| 5.938 | 0.375 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s4/I2 |
| 6.399 | 0.461 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s4/F |
| 6.774 | 0.375 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s1/I0 |
| 6.910 | 0.136 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s1/O |
| 7.285 | 0.375 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s/I1 |
| 7.371 | 0.086 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_26_s/O |
| 7.746 | 0.375 | tNET | RR | 1 | mem_rdata_26_s4/I1 |
| 8.262 | 0.516 | tINS | RR | 1 | mem_rdata_26_s4/F |
| 8.637 | 0.375 | tNET | RR | 1 | mem_rdata_26_s2/I0 |
| 9.164 | 0.526 | tINS | RR | 3 | mem_rdata_26_s2/F |
| 9.539 | 0.375 | tNET | RR | 1 | core/mem_rdata_latched_10_s8/I1 |
| 10.055 | 0.516 | tINS | RR | 3 | core/mem_rdata_latched_10_s8/F |
| 10.430 | 0.375 | tNET | RR | 1 | core/n5637_s8/I1 |
| 10.946 | 0.516 | tINS | RR | 1 | core/n5637_s8/F |
| 11.321 | 0.375 | tNET | RR | 1 | core/n5637_s7/I2 |
| 11.782 | 0.461 | tINS | RR | 3 | core/n5637_s7/F |
| 12.157 | 0.375 | tNET | RR | 1 | core/n5231_s15/I1 |
| 12.674 | 0.516 | tINS | RR | 2 | core/n5231_s15/F |
| 13.049 | 0.375 | tNET | RR | 1 | core/n2082_s10/I2 |
| 13.510 | 0.461 | tINS | RR | 1 | core/n2082_s10/F |
| 13.885 | 0.375 | tNET | RR | 1 | core/n2082_s5/I1 |
| 14.401 | 0.516 | tINS | RR | 4 | core/n2082_s5/F |
| 14.776 | 0.375 | tNET | RR | 1 | core/n2085_s1/I2 |
| 15.237 | 0.461 | tINS | RR | 2 | core/n2085_s1/F |
| 15.612 | 0.375 | tNET | RR | 1 | core/n2086_s0/I0 |
| 16.139 | 0.526 | tINS | RR | 1 | core/n2086_s0/F |
| 16.514 | 0.375 | tNET | RR | 1 | core/mem_rdata_q_20_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_in | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 3817 | clk_in_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | core/mem_rdata_q_20_s0/CLK |
| 10.311 | -0.064 | tSu | 1 | core/mem_rdata_q_20_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 18 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 8.256, 51.158%; route: 7.500, 46.472%; tC2Q: 0.382, 2.370% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:| Slack | -6.202 |
| Data Arrival Time | 16.514 |
| Data Required Time | 10.311 |
| From | core/mem_addr_26_s0 |
| To | core/mem_rdata_q_27_s0 |
| Launch Clk | clk_in[R] |
| Latch Clk | clk_in[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_in | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3817 | clk_in_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | core/mem_addr_26_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 2 | core/mem_addr_26_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | itcm_valid_s2/I0 |
| 1.659 | 0.526 | tINS | RR | 6 | itcm_valid_s2/F |
| 2.034 | 0.375 | tNET | RR | 1 | itcm_valid_s3/I3 |
| 2.296 | 0.262 | tINS | RR | 4 | itcm_valid_s3/F |
| 2.671 | 0.375 | tNET | RR | 1 | core/n1614_s2/I0 |
| 3.198 | 0.526 | tINS | RR | 5 | core/n1614_s2/F |
| 3.573 | 0.375 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I1 |
| 4.089 | 0.516 | tINS | RR | 41 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
| 4.464 | 0.375 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
| 4.726 | 0.262 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
| 5.101 | 0.375 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
| 5.562 | 0.461 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
| 5.938 | 0.375 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s4/I2 |
| 6.399 | 0.461 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s4/F |
| 6.774 | 0.375 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s1/I0 |
| 6.910 | 0.136 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s1/O |
| 7.285 | 0.375 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_26_s/I1 |
| 7.371 | 0.086 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_26_s/O |
| 7.746 | 0.375 | tNET | RR | 1 | mem_rdata_26_s4/I1 |
| 8.262 | 0.516 | tINS | RR | 1 | mem_rdata_26_s4/F |
| 8.637 | 0.375 | tNET | RR | 1 | mem_rdata_26_s2/I0 |
| 9.164 | 0.526 | tINS | RR | 3 | mem_rdata_26_s2/F |
| 9.539 | 0.375 | tNET | RR | 1 | core/mem_rdata_latched_10_s8/I1 |
| 10.055 | 0.516 | tINS | RR | 3 | core/mem_rdata_latched_10_s8/F |
| 10.430 | 0.375 | tNET | RR | 1 | core/n5637_s8/I1 |
| 10.946 | 0.516 | tINS | RR | 1 | core/n5637_s8/F |
| 11.321 | 0.375 | tNET | RR | 1 | core/n5637_s7/I2 |
| 11.782 | 0.461 | tINS | RR | 3 | core/n5637_s7/F |
| 12.157 | 0.375 | tNET | RR | 1 | core/n5637_s4/I1 |
| 12.674 | 0.516 | tINS | RR | 11 | core/n5637_s4/F |
| 13.049 | 0.375 | tNET | RR | 1 | core/n2079_s10/I1 |
| 13.565 | 0.516 | tINS | RR | 3 | core/n2079_s10/F |
| 13.940 | 0.375 | tNET | RR | 1 | core/n2079_s5/I2 |
| 14.401 | 0.461 | tINS | RR | 1 | core/n2079_s5/F |
| 14.776 | 0.375 | tNET | RR | 1 | core/n2079_s2/I0 |
| 15.302 | 0.526 | tINS | RR | 1 | core/n2079_s2/F |
| 15.677 | 0.375 | tNET | RR | 1 | core/n2079_s0/I2 |
| 16.139 | 0.461 | tINS | RR | 1 | core/n2079_s0/F |
| 16.514 | 0.375 | tNET | RR | 1 | core/mem_rdata_q_27_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_in | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 3817 | clk_in_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | core/mem_rdata_q_27_s0/CLK |
| 10.311 | -0.064 | tSu | 1 | core/mem_rdata_q_27_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 18 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 8.256, 51.158%; route: 7.500, 46.472%; tC2Q: 0.382, 2.370% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |